Typically, a digital imager array includes a focal plane array of pixel cells, each one of the cells including a photosensor, e.g. a photogate, photoconductor, or a photodiode. In a CMOS imager a readout circuit is connected to each pixel cell which typically includes a source follower output transistor. The photosensor converts photons to electrons which are typically transferred to a floating diffusion region connected to the gate of the source follower output transistor. A charge transfer device (e.g., transistor) can be included for transferring charge from the photosensor to the floating diffusion region. In addition, such imager cells typically have a transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference. The output of the source follower transistor is gated as a pixel output signal by a row select transistor.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524, and U.S. Pat. No. 6,333,205, each assigned to Micron Technology, Inc. The disclosures of each of the forgoing patents are hereby incorporated by reference in their entirety.
With reference to FIGS. 1, 2 and 3, which respectively illustrate a top-down view, a cross-sectional view and electrical circuit schematic of a conventional CMOS pixel sensor cell 100 when incident light 187 strikes the surface of a photodiode photosensor 120, electron/hole pairs are generated in the p-n junction of the photodiode (represented at the boundary of n− accumulation region 122 and p+ surface layer 123). The generated electrons (photo-charges) are collected in the n-type accumulation region 122 of the photodiode 120. The photo-charges move from the initial charge accumulation region 122 to a floating diffusion region 110 via a transfer transistor 106. The charge at the floating diffusion region 110 is typically converted to a pixel output voltage by a source follower transistor 108 and subsequently output on a column output line 111 via a row select transistor 109.
Conventional CMOS imager designs, such as that shown in FIGS. 1 and 2 for pixel cell 100, provide only approximately a fifty percent fill factor, meaning only half of the pixel 100 is utilized in converting light to charge carriers. As shown, only a small portion of the cell 100 comprises a photosensor (photodiode) 120. The remainder of the pixel cell 100 includes the isolation regions 102, shown as STI regions in a substrate 101, the floating diffusion region 110 coupled to a transfer gate 106′ of a transfer transistor 106, and source/drain regions 115 for reset 107, source follower 108, and row select 109 transistors having respective gates 107′, 108′, and 109′. Moreover, as the total pixel area continues to decrease (due to desired scaling), it becomes increasingly important to create high sensitivity photosensors that utilize a minimum amount of surface area or to find more efficient layouts on the pixel array for the non-photosensitive components of the pixel cells to provide increased photosensor areas.
In addition, conventional storage nodes, such as floating diffusion region 110, have a limited amount of charge storage capacity. Once this capacity is reached, a pixel cell becomes less efficient. Once the charge storage capacity is exceeded, an undesirable phenomenon occurs, whereby the “over-capacity” charges escape to undesirable parts of the pixel cell 100 or to adjacent pixel cells. One suggested solution for dealing with this limited charge storage capacity is to utilize a capacitor which is connected with the floating diffusion region. The problem with this solution, however, is that a capacitor on a pixel cell takes up space that could otherwise be used to increase the size of the photosensor, thereby decreasing the potential fill factor for the pixel cells and overall array.
Accordingly, there is a desire for an efficient pixel cell array architecture which has an improved fill factor and charge storage capacity.